As semiconductor micro-processing technology advances, with the conventional element isolation method according to the LOCOS method, it is becoming difficult to fabricate in a narrower width, that is, in a minute area and at a high level of precision, a plurality of element formation areas (hereinafter, also referred to simply as active areas) to be provided in a unit chip area in which elements are to be formed. In order to solve such a problem, element isolation is conventionally carried out by STI, in which shallow trenches are formed in the semiconductor substrate, and a silicon oxide film is embedded therein.
For example, a semiconductor memory device formed in a single chip is usually provided with a memory cell array area, in which a plurality of memory cells are provided in a matrix, and a logic circuit area, in which a logic circuit for controlling operation of the memory cells is arranged. In the case where these constructions are element-isolated by STI, in general, one, two, or more arbitrarily suitable areas having one, two, or more types of width (area) such as a large isolation area provided in a large area that electrically isolates the memory cell array area from the logic circuit area and that separates them in distance, and a small isolation area that isolates minute elements formed in the memory cell array area from one another, are set.
In a step of planarizing the film structure in the fabrication method of STI, in general, a chemical mechanical polishing (CMP) step is often carried out, and this CMP step often causes an undesirable recess, called dishing, to occur in an oxide film that is embedded in the trench section, especially in the large isolation area.
When dishing occurs in STI, for example, a film material of polysilicon film formed in a gate electrode formation step remains in this dishing. Consequently, there is a risk of deterioration of the electrical characteristics of an element formed in the active area.
Moreover, to attempt removal of the film material remaining in the dishing, so-called over etching needs to be carried out. However, there is, for example, a risk of damaging the gate oxide film formed in the active area due to such over etching, causing deterioration of the electrical characteristics of the element.
In order to solve such problems relating to STI dishing, various kinds of STI fabrication methods have been proposed.
For example, a method for STI formation is known (refer to Unexamined Japanese Patent Publication No. Hei 8-181108) in which, with an object of preventing occurrence of a corrupted portion in the end section of an STI element isolation part due to dishing occurrence, and to avoid problems such as the occurrence of a parasitic transistor due to electric field concentration, and a decrease in dielectric breakdown withstand voltage, a film of a substance having a high etching rate for wet etching is formed on a semiconductor substrate, the substance, which has a high etching rate, in the area corresponding to the element isolation area and the semiconductor substrate are selectively etched by anisotropic etching, and an insulating film is formed on side walls and on a bottom section of the trench formed as a result of this etching, and, having formed a planarization film, wet etching is carried out.
Moreover, there is also a known method for STI formation (refer to Unexamined Japanese Patent Publication No. Hei 9-045687) in which, with an object of preventing dishing from occurring, an insulating film is formed only on the substrate surface excluding inside the trench section formed in the silicon substrate, and silicon oxide films, the film-thickness of which are different inside the trench section and on the insulating film, are formed making a use of substrate dependency, and furthermore, the silicon oxide film that fills in the trench section is planarized making use of a difference in etching rates in an etching step.
According to the STI formation methods disclosed in these Patent Documents, there are problems that the formation steps are complex and the formation work-hours are many.
Therefore, there is a demand for a technique for providing, in a simple process, an element isolation structure that can prevent dishing from occurring and secure excellent in-plane uniformity without detracting from the electrical characteristics of the element formed in the active area, and that can cope with the advancement in micro processing technology.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.